1. Field of the Invention
The present invention relates in general to a duty correction circuit, and in particular to a duty correction circuit which can enable input clocks used in the DDR DRAM and RAMBUS DRAM to have a duty approximately equal to 50%.
2. Description of the Background Art
In general, a DDR DRAM does not correct a duty. A duty error of an input clock has a specification of xc2x15%, and a jitter has a specification of xc2x110%. That is, when the frequency is 166 MHz, the jitter specification is xc2x1600 ps, and the duty error of the input clock is xc2x1300 ps. When the duty error of the input clock is reflected to an output clock and an output data as it is, the considerable jitter specification is xc2x1300, and thus there is little margin in the circuit design.
Accordingly, many duty correction circuits have been suggested. However, it is difficult to form a duty correction circuit of a CMOS clock in a digital type. Such duty correction circuits correct the duty when a clock signal clk and a clock bar signal clkb have the same duty error. In the case that the clock signal clk and the clock bar signal clkb have different duty errors, namely a completely complementary relationship, for example when the duty of the clock signal clk is 40% and the duty of the clock bar signal clkb is 60%, the aforementioned duty correction circuits correct only one of the duties, but not the other.
Accordingly, it is an object of the present invention to provide a circuit for correcting a duty of a CMOS clock.
Another object of the present invention is to provide a duty correction circuit which can reduce a layout area on a semiconductor IC chip surface.
Still another object of the present invention is to provide a duty correction circuit that can be easily designed.
In order to achieve the above-described objects of the invention, there is provided a duty correction circuit including: a duty check block for determining a duty of a clock signal, and generating a control signal indicating the determination result; and a duty correction block for receiving the clock signal or a clock bar signal having a phase difference of 180xc2x0 with respect to the clock signal, correcting a duty of one of the clock signal or clock bar signal according to the control signal from the duty check block, and outputting the duty-corrected signal. The duty check block determines whether the duty of the clock signal is 50%, below 50% or over 50%. Here, the duty correction unit corrects the duty of the clock signal when the duty of the clock signal is below 50%, corrects the duty of the clock bar signal when the duty of the clock signal is over 50%, and outputs the clock signal or clock bar signal without correction when the duty of the clock signal is 50%.
The duty check block includes: a first switch controlled according to the clock signal; a second switch controlled according to the clock bar signal; a first capacitor charged or discharged by the on or off state of the first switch; and a second capacitor charged or discharged by the on or off state of the second switch. In addition, the duty check block further includes a comparator for comparing a voltage applied to the first capacitor with a voltage applied to the second capacitor, and generating the control signal.
The duty correction unit includes: a clock signal correction unit enabled according to the control signal for correcting the duty of the clock signal, when the duty of the clock signal is below 50%; and a clock bar signal correction unit enabled according to the control signal for correcting the duty of the clock bar signal, when the duty of the clock signal is over 50%. The clock signal correction unit includes: a first phase blending circuit for enabling the clock signal to have a predetermined slope; a first delay circuit for delaying the clock signal for a predetermined time; and a second phase blending circuit for enabling the output signal from the first delay circuit to have a predetermined slope. The first phase blending circuit and the second phase blending circuit have their output terminals electrically connected. The clock bar signal correction unit includes: a third phase blending circuit for enabling the clock bar signal to have a predetermined slope; a second delay circuit for delaying the clock bar signal for a predetermined time; and a fourth phase blending circuit for enabling the output signal from the second delay circuit to have a predetermined slope. The third phase blending circuit and the fourth phase blending circuit have their output terminals electrically connected.
Preferably, the duty correction circuit further includes a clock buffer block for receiving the output signal from the duty correction unit, and generating a new clock signal and clock bar signal, which have a phase difference of 180xc2x0 from each other. The clock buffer unit includes two inverter chains for receiving the output signal from the duty correction unit. One inverter chain comprises an even number of inverters, and the other inverter chain comprises an odd number of inverters.
In accordance with the present invention, the duty correction operation is performed after checking up the duty error of the input clocks used in a high speed memory device, and confirming whether the clocks have a duty over 50% or below 50%. That is, one clock is duty-corrected by using a circuit for sensing which of the clocks has the error in which side, and then two clocks having a phase difference of 180xc2x0 are newly generated by using the corrected clock signal. Therefore, the duty of the CMOS clock can be precisely corrected in the above-described construction. In addition, the duty correction circuit has a simpler structure than an analog-type duty correction circuit, thereby reducing the layout area and simplifying the design.